Rtl Design Engineer - Barcelona, España - Esperanto

Esperanto
Esperanto
Empresa verificada
Barcelona, España

hace 3 semanas

Isabel García

Publicado por:

Isabel García

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Descripción

Responsibilities:


  • Own or assist in the development of key modules in uncore blocks like NoC or debug.
  • Perform performance studies, including area and power estimation.
  • Write microarchitecture specifications
  • Work with design verification team to draft test plans, debug test failures and to ensure functional correctness
  • Synthesize RTL to logic gates using standard CAD tools and build timing and area constraints
  • Interact closely with physical design team to guarantee proper backend implementation
  • Support Silicon bringup and diagnostics
  • Support simulation and emulation infrastructure
  • Qualifications
  • BS/MS in CS/EE or related technical field
- +5 years in ASIC/SOC design and Verilog RTL coding experience

  • Completed ASIC/SOC design projects with successful tapeouts
  • Knowledge of logic design principles along with timing and power implications
  • Additional valuable experience
  • Experience in industrial standard ASIC/SOC CAD tools for simulation, synthesis, debug, timing analysis and power estimation
  • Excellent verbal and written communication skills
  • Experience in Python and/or bash scripts
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