- Designer will take blocks through the entire front end design process including:
- Creating specification based on architectural/system requirements
- Defining and documenting micro-architectural solution
- Implementing the RTL Verilog code
- Collaborating with verification to develop an appropriate testplan to verify the implementation, debug any issues, and ensure testing coverage is complete
- Collaborating with physical design to resolve timing, area, power, and routing issues in the implementation
- Supporting post-silicon bring up in resolving any issues that arise in the designer's block
- Designer will participate in internal reviews to ensure adherence to the company's design processes and guidelines and to improve those processes and guidelines
- In order to deliver top quality chips, we must work cross-functionally. The candidate will work closely with all parts of engineering: Architecture, Verification, Physical Design, Post-Silicon Bring Up, and Program Management
- We are a results-driven team. The candidate must accurately predict schedules and track their own progress and identify appropriate cross-functional requirements
- MS in Electrical Engineering or equivalent
- 10+ years ASIC design experience
- Experience with RISC-V based systems or similar
- Strong knowledge and experience in fixed and floating-point standard numerical formats and arithmetic implementation using them
- Strong knowledge of the main core processors sub-systems and concepts, pipelines, data and instruction caches, scoreboards, etc.
- Strong knowledge of ASIC and/or FPGA design methodology and should be well versed in Verilog, front-end design, simulation, synthesis, timing, power analysis and verification CAD tools
- Excellent verbal and written communication skills
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rtl core processor design engineer - Barcelona, España - Esperanto
Descripción
We are looking for an RTL designer to do high-speed digital design for a RISC-V based processor. This is an opportunity to do world-class ASIC work on advanced process technologies.Responsibilities#J-18808-Ljbffr
