Fpga Research Engineer - Barcelona, España - Barcelona Supercomputing Center (BSC)

Barcelona Supercomputing Center (BSC)

Empresa verificada

Barcelona, España

hace 2 semanas

Publicado por:

Isabel García

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Descripción

Job Reference:

359_24_CS_HWE_RE1
Position:
FPGA Research Engineer (RE1)
Closing Date:
Sunday, 16 June, 2024
Reference: 359_24_CS_HWE_RE1
Job title: FPGA Research Engineer (RE1)
About BSC
The Barcelona Supercomputing Center
Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads largescale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 900 staff from 55 countries.
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BSC-CNS YouTube Channel
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Context And MissionKey Duties*
Design and development FPGAbased solutions
Contribute to the characterization of the FPGAbased infrastructure
Provide users' support from the FPGA design and development perspective
Conttribute to the development of tools for facilitating the usability of FPGAbased emulation platform Debugging and Troubleshooting complex hardware designs (JTAG, ILA, etc) and optimizing the FPGA designs at synthesis, place and route, timing closure, verification, validation
Requirements:
Education
Telecommunication, Electrical, Computer Architecture Engineering or similar
PhD in computer architecture, telecommunciation or similar
Essential Knowledge and Professional Experience
Deep handson experience with FPGAs hardware, software, and toolchain
Xilinx FPGA Toolchain: Vivado, Vitis, SDSOC on Alveo, Versal, or Ultrasclae+
Peripheral IPs: DDR and HBM, PCIe, CXL, Ethernet, DMA, UART, nVME, etc
Hardware/Software codesign experience: FPGA and Processor
HDL: VHDL, Verilog, SystemVerilog
HLS: Vivado HLS and/or OpenCL and/or Bluespec
Competences
Soft skills: Selfcontrol, proactive, responsible, collaborative, and quickly adaptable to new topics
Research publications in relevant venues (e.g., MICRO, ISCA, HPCA, FPGA, FPL, FCCM,)
Processor microarchitecture based on riscv and experience with emulating riscv designs on FPGAs (Optional)
System software and Operating System flow on

FPGA:
Linux kernel porting, device drivers, device tree configuration, bootloader configuration (good understanding of Linux Kernel) (Optional)

Conditions

The position will be located at BSC within the Computer Sciences Department
We offer a fulltime contract (37.5h/week), a good working environment, a highly stimulating environment with stateoftheart infrastructure, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
Duration: Openended contract due to technical and scientific activities linked to the project and budget duration
Holidays: 23 paid vacation days plus 24th and 31st of December per our collective agreement
Starting date: June

Applications procedure and process- A full CV in English including contact details

A Cover Letter with a statement of interest in English, including two contacts for further references
Applications without this document will not be considered

At BSC we are seeking continuous improvement in our recruitment processes, for any suggestions or feedback/complaints about our Recruitment Processes, please contact recruitment [at] bsc [dot] es.

For more information follow this link

DeadlineOTM-R principles for selection processes**- BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.