Verification Engineer for Vector Accelerators - Barcelona, España - Barcelona Supercomputing Center (BSC)

Barcelona Supercomputing Center (BSC)
Barcelona Supercomputing Center (BSC)
Empresa verificada
Barcelona, España

hace 1 mes

Isabel García

Publicado por:

Isabel García

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Descripción

Job Reference:


  • 54_23_CS_V_ RE2
    Position:
  • Verification engineer for vector accelerators (RE2)
    Closing Date:
  • Thursday, 16 February, 2023
    Reference: 54_23_CS_V_ RE2
    Job title: Verification engineer for vector accelerators (RE2)
    About BSC
  • The Barcelona Supercomputing Center
  • Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 770 staff from 55 countries.
  • Look at the BSC experience:
  • BSC-CNS YouTube Channel
  • Let's stay connected with BSC Folks
  • We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research.
    Context And Mission
  • BSC is looking for talented and motivated professionals with expertise in Design Verification for a European HPC accelerator in the context of the European Processor Initiative (EPI) Project and other related research projects. The design is based on RISC-V architecture. BSC contributes a RISC-V vector accelerator to the EPI project and verifying its functional correctness is key for success.
    Key Duties
  • You will use your design and verification expertise to verify complex digital designs, focused on vector units, other accelerators and scalar processors.
  • You will collaborate closely with design and verification engineers in active projects and perform handson verification, and contribute to design, build, and integrate the designs.
  • Using your UVM, SystemVerilog and problemsolving skills, you will build efficient and effective verification environments that exercise processor designs through their cornercases and expose all types of bugs.
  • You will be involved in the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition and others.
  • You will automatize the processes by creating and maintaining verification & postprocessing scripts for verification, triaging, coverage and debugging.
  • You will train others in the configuration, deployment, use and/or maintenance of verification software, scripts and workflows.
  • You will create and maintain C and Assembly tests for the verification of a RISCV Vector Accelerator to be used in regressions and to improve coverage.
  • You will perform Gate-Level Simulation of synthesized netlists.

Requirements:


  • Education
  • MS degree in Electrical Engineering, Computer Engineering, or equivalent, with demonstrable professional experience.
  • Essential Knowledge and Professional Experience
  • Experience with the full verification life cycle from test planning to signoff.
  • Working knowledge of Universal Verification Methodology (UVM), writing test plans, simulating, debugging, and documenting results
  • Knowledge of and experience with industrystandard simulators (Model/QuestaSim, VCS, etc.), revision control systems and regression systems.
  • Experience in some of the following key DV methodologies: UVM, cosimulation, SystemVerilog Assertions, functional coverage, Assembly/Cbased random/constrainedrandom Verification, gatelevel simulation
  • Experienced in developing a DV plan based on Functional Specification, create and build the necessary verification test bench/infrastructure, develop tests and verify the design.
  • Experience in the creation and implementation of validation plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Experience in the analysing of coverage reports and improving results to reach closure. In particular, writing C and Assembly tests that target specific coverpoints on simulation.
  • Strong debugging and triaging skills and ability to work with design engineers to deliver functionally correct design blocks, execute tests, analyze data, and prepare reports summarizing results and statistics.
  • Strong scripting experience using scripting languages like Python, Perl, Bash or Tcl to perform support adjustments and customization of design and verification flows. Familiarity with Linux.
  • Experience in the implementation of SystemVerilog UVM testbenches for a complex digital design, coupling with a reference model for cosimulation.
  • Experience in the analysing of coverage reports and improving results to reach closure.
  • Experience in adapting UVM testbenches for Gate-Level simulation, and debugging gatelevel simulations.
  • Good knowledge of the R
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