Lead Verification Engineer - Barcelona, España - Akuaro Work SLU

Akuaro Work SLU
Akuaro Work SLU
Empresa verificada
Barcelona, España

hace 3 semanas

Isabel García

Publicado por:

Isabel García

beBee Recruiter
Descripción

Our partner, a direct collaborator in the RISC-V architecture, is actively involved in a fierce battle against the "monopoly" ARM, leading companies like Google to consider shifting their future processors towards this architecture.

This move addresses the growing need to incorporate AI into chips for mobiles, tablets, smartwatches, and ultimately any IoT device in the future.

They are currently seeking to add talented individuals like you to their team.


Today, they boast highly specialized professionals in this field and have forged alliances with key industry partners, in addition to running their own training academy to nurture critical talent for their business.

They are currently looking to onboard Senior Talent and Leads, and they invite you to be part of this exciting journey as a
Verification Leader


Verification Leader, your role involves leading the Verification Team to guarantee the accuracy and functionality of intricate digital designs at the Register Transfer Level (RTL), adhering to specifications.

You'll employ advanced verification techniques and tools to validate designs meticulously, ensuring their correctness and performance.


Job description (responsibilities):


  • Team Leadership
  • Verification Planning
  • Testbench Development
  • Verification Environment Setup
  • Test Execution and Debugging
  • Coverage Analysis
  • Verification Methodologies

Desired knowledge:


  • Experience leading a team
  • Proficiency in SystemVerilog and UVM
  • Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
  • Experience with simulation and simulation tools
  • Knowledge of revision control methodology and tools (git, svn)
  • Experience in block level and subsystem or top level verification
  • Experience with formal and dynamic verification
  • Strong problemsolving skills and attention to detail
  • Excellent communication and teamwork abilities

Preferred/Valued knowledge:

Knowledge of RISC-V and RISC-V Vector Extension

Experience with GLS

  • Knowledge of the JIRA tool
  • Experience with ASIC and FPGA design
Knowledge of C++
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