Fpga Digital Design Engineer - Paterna, España - Photonic Sensors & Algorithms

Photonic Sensors & Algorithms

Empresa verificada

Paterna, España

hace 1 semana

Publicado por:

Isabel García

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Descripción

Everything we do is designed to challenge the limits of imaging and sensing technologies. We thrive on excellence in execution while having fun pushing the boundaries of what an image can express.

We offer a permanent contract with a competitive salary and career opportunity in a growing company with global coverage and ambition.

There's still a lot of work to be done. We need best in class optical designers, software, parallel computing, heterogeneous computing and digital image processing experts.

We'd like to hear from you If you have experience or a PhD in one of the following fields:
Computer Science, Telecommunication Engineering, Parallel Computing, Electronic Engineering, Physics, Mathematics.

FPGA Digital Design Engineer required to join our team developing an innovative low-power consumption ASIC to obtain high-quality depth maps and images by processing real-time video frames captured by apiCAM, our leading, state-of the-art 3D camera.

apiCAM offers simultaneously 2D and 3D with a single lens, currently at 30 fps (frames per second), higher in the future.

apiCAM is already available in commercial products for Medical Imaging, Robotics, Industry 4.0 and aims to be in the next generation of XR-glasses, Tablets, PCs and Smartphones.

You will join our Algorithms team, specifically the group porting our state-of-the-art depth and imaging algorithms to FPGAs and finally to an ASIC.

This team is part of our R&D Department with experts in Physical-Optics, Image-Processing, Algorithms, Software and Industrial Automation.

_Responsibilities_

Porting blocks of our current algorithms to FPGAs.
Development of digital image and depth computation IPblocks using Xilinx tools for FPGAs.
Analysis, design, and integration of low power consumption but the most efficient possible digital designs for realtime depth mapping.
Collaborate with other members of the Digital Design and Verification Engineering Groups to jointly redefine and optimize complete designs including multiple IPblocks.

_Knowledge Requirements_

Bachelor and/or Master degree in Telecommunication, Electronics, Computer Science or related fields.
HDLs-Hardware Description Languages (Verilog and/or VHDL) and integration of IPblocks.
Version control software such as Git or SVN.
Ability to understand signal processing algorithms in software such as Matlab, Python and/or C++.
Motivated, willing to work in a team and to face big challenges such as the design, verification, and manufacturing of an ASIC from the very beginning.

_Desirable Experience_

Knowledge of basic FPGA architectures, operation modes (sequential, parallel or hybrid).
State machines.
Finite precision modelling in Matlab or others.

_We offer_

Competitive salary according to your experience.
Flexible working hours (12 teleworking days per week).
Flexible compensation plan (restaurant tickets, transport, childcare, health insurance ).
Professional career plan within the company. Lifelong learning.
Dynamic startup environment.
Fix contract and professional stability within a demanding but friendly working environment.
Join us_

We create disruptive technologies. We enjoy what we do and aim for global leadership in our disciplines. We live innovation every day, and we invite you to explore the opportunities offered. Come and discover your capabilities