Senior Design Verification Engineer - Barcelona, España - European Recruitment
Descripción
The company is a well-established Semiconductor organisation supplier of RISC-V IP cores who are looking for Verification Engineers at all levels to join their team onsite in Bareclona, Spain.
Responsibilities:
- Working on the verification of a RISC-V design for an advanced technology node.
- Focusing on Vector Instructions
- RISC-V base ISA, RISC-V privileged ISA, Cache coherency protocols and full SoC verification
Qualifications:
- 2+ years of Industry experience.
- Knowledge of RISC-V, UVM or Formal Verification
- Excellent Verilog/System Verilog programming skills.
- Scripting experience (Python, Perl, TCL, shell programming) highly desirable.
Keywords:
UVM / ASIC /System Verilog / Verilog / Python / Perl /RISC-V
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