Senior Formal Verification Engineer - Barcelona, Catalonia

We are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise in digital design verification. · Masters or PhD in Computer Science, Electrical Engineering, or a related field required. · ...

We are looking for a Digital IC Verification Engineer with hands-on experience using Cadence verification tools to verify complex digital ICs and SoCs. · Develop verification plans from design specifications and micro-architecture documents · Build and maintain SystemVerilog/UVM ...

As a Functional Verification Engineer , you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. · Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Sim ...

As Functional Verification Engineer you will interface with architecture design physical implementation software teams to ensure systems perform at highest level. · ...

We are seeking an experienced Senior Verification Engineer for our Verification Team. The ideal candidate will have a strong background in SystemVerilog and UVM. · Develop and apply advanced verification methodologies. · Build testbenches, run simulations. · ...

Are you passionate about microprocessor architecture and ready to make an impact as a Senior Verification Engineer? · Interested in a company that's pushing the boundaries of high-performance RISC-V cores? · ...

We're hiring a Senior Verification Engineer to join a well-established CPU architecture company building high-performance configurable processor IP used in real-world products. · Verifying complex RTL designs against architectural intent · Writing and maintaining SystemVerilog / ...

This is a job for a Senior Verification Engineer to lead RTL verification for next-gen AI/ML compute platforms at a fast-growing European semiconductor company. · Master's or PhD in EE/CS · 5–8+ years in digital verification (SystemVerilog/UVM) · Strong scripting and simulation t ...

The Role: · As a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems. · Responsibilities: · Work closely with system architects and design team to establish formal verification environment and sett ...

The Role : · As a Senior Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, ...

As a Staff Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation ...

We're hiring a Senior Verification Engineer to work on high-performance CPU designs at an established processor IP company. This is a hands-on role with ownership from RTL block verification through to full-chip sign-off on designs that ship in real products. · Verify complex RTL ...

The opportunity to build a cloud AI deployment platform that will power next generation AI systems. · A collaborative, innovation-driven environment with significant autonomy and ownership. · Hybrid work model with flexible scheduling.We're looking for exceptional engineers ready ...

+We are looking for a Digital IC Verification Engineer with hands-on experience using Cadence verification tools to verify complex digital ICs and SoCs.+ · +Develop verification plans from design specifications and micro-architecture documents. · Build and maintain SystemVerilog/ ...

We are seeking a Staff Verification Engineer to join our innovative team in Ghent, Belgium. As a key member of our verification team, you will be responsible for developing detailed test and coverage plans based on architecture and micro-architecture requirements. · Reading and a ...

Mixed Signal Digital Verification Engineer assists on the Analog Design and Analog-Digital interface definition design validation verification and integration of mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. · ...

The IFAE announces the opening of a position for the LST Project to be located at La Palma. · ...

The Verification & Validation (V&V) Engineer is responsible for planning, executing and documenting all verification and validation activities for the Large-Sized Telescope (LST) in La Palma. The V&V Engineer will develop and maintain the Verification Control Matrix (VCM). Prepar ...

Nuestro partner busca un Senior Verification Engineer para unirse al equipo de verificación. · Últimas palabras: El trabajador tendrá horarios flexibles, · salario competitivo, · y oportunidades de crecimiento en una empresa líder. · ...

We are looking for a Senior Systems Engineer with strong experience in leading complex technical projects and driving the full systems engineering lifecycle. · ...