Intern (Technical) - España - Synopsys

Synopsys

Empresa verificada

España

hace 2 semanas

Publicado por:

Isabel García

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Descripción

48730BR

CANADA
Canada, CANADA
Ontario
Kanata, CANADA
Ontario
Markham, CANADA
Ontario
Mississauga, CANADA
Ontario
Nepean, CANADA
Ontario
Toronto, CANADA
Ottawa

Job Description and Requirements

Synopsys DDR PHY Engineering Intern Position**This position is a 12 or 16 month internship in Ottawa starting May 6th, sitting in our Nepean office.

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ABOUT THE POSITION
You would be part of the Synopsys IP development group. The Solutions Group is dedicated to providing our customers with a broad portfolio of leading-edge IP.

The Synopsys IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems.

Within the Solutions Group, the DDR PHYsical Layer (PHY) Group delivers leading edge DDR, LPDDR and HBM PHY solutions to our customers, whose products are used in all kinds of computing devices including game consoles, graphics processors, smartphones, servers, and many more.
The DDR PHY development team has an expanding number of ongoing and new development projects of varying duration and complexity. In this position, you will have the amazing opportunity to be part of the team which is uniquely positioned to provide you with a broad overview of the complexities, processes and activities associated with DDR PHY development.
The Synopsys DDR PHY IP is complex design consisting of a combination of Digital, Analog, and Firmware components. It has been architected to provide customers with a highly configurable and flexible DDRPHY implementation. This flexibility requires programming the DDRPHY IP in a configuration specific way which must support customer specific use models.
To enhance the customer experiences and ensure a correct DDRPHY configuration, a 'C' based tool has been developed. This tool has become essential for both customers and internal users of the DDRPHY IP.
As part of our team, you will:
Own the development of new features and updates to the DDRPHY initialization configuration tool using Verilog, System Verilog, UVM methodology, C/C++, Scripting (e.g. Python/Perl/Tcl)
Provide support to the user community.
Interact regularly with the Architecture, RTL, Verification, Analog, and Firmware teams.
Get RTL exposure, work with a member of the RTL design team to learn their methodology and take on RTL tasks.
Gain hands on learning about the complexities associated with the development of next generation DDRPHY products.
Perform RTL and gatelevel simulations and associated debugging on production PHY releases.
Develop and assume ownership for the development and automation of various tasks.
Be responsible for completing work on cuttingedge projects.
SKILLS AND EXPERIENCE REQUIREMENTS
3rd year in Electrical Engineering or equivalent
Knowledge, experience and interest in semiconductor design
Basic knowledge of scripting languages, Verilog, Jira, C
Ability to learn and understand the technical aspects of an IP development project
Selfmotivated and not afraid to take on a large task Excellent communications skillsAt Synopsys, we're at the heart of the innovations that change the way we work and play. Selfdriving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Job Category
Interns/Temp